1. Field of the Invention
The present invention relates to an image decoding apparatus which decodes compression-encoded image information on the basis of encoded code information and reference pixel information, and an image decoding method therefor. More particularly, the present invention relates to an image decoding apparatus which can achieve a high-speed decoding process by suppressing data input/output to/from an external memory along with the decoding process, an image decoding method therefor, and a printing apparatus.
2. Description of the Related Art
These days, devices such as a personal computers (PC) and copying machines are very common. Image forming apparatuses such as an inkjet apparatus and electrophotographic apparatus for printing digital images have rapidly been developed and have become popular. Especially as devices attain more advanced functions, they handle color data more frequently. Along with this trend, image forming systems such as a color inkjet system and an color electrophotographic system have been developed.
An image forming system adopting the inkjet method will be exemplified.
Such an image forming system often comprises an image forming controller and image forming engine. FIG. 4 shows an example of this image forming system. An image forming controller 115 in an image forming system 116 has an interface for exchanging image information and various kinds of control information with a printer driver 411 in a host PC 101. The image forming controller 115 generates image forming data based on input image information. An image forming engine 114 in the image forming system 116 conveys a print medium, drives a carriage, and controls the print head to form an image.
The image forming system comprises an image decoding apparatus which decompresses image information by decoding encoded code information. As an encoding method employed in the image forming system, there are proposed many encoding methods using the correlation with neighboring pixel values, like a run-length code or delta row code. The run-length code is used to encode the run length and pixel value when the same pixel value runs in the raster direction (horizontal direction). The delta row code is used to encode the run length when the same pixel value as that of an immediately preceding (upper) raster runs in the vertical direction.
These encoding methods utilize the fact that pixels having the same pixel value (close pixel values) are highly likely to run in the horizontal or vertical direction. A method of obtaining a high compression ratio by performing encoding using the correlation between the horizontal and vertical directions has also been developed (see, e.g., Japanese Patent Laid-Open No. 2002-223360). The encoding method disclosed in Japanese Patent Laid-Open No. 2002-223360 executes encoding by referring to left and upper pixels, and is particularly suited to an image forming system which processes a raster scan image. When upper, upper left, and upper right pixels are used as reference pixels, a decoding process for one raster requires pixels of one upper raster as reference pixels.
A data flow in the image forming controller will be explained with reference to FIG. 5.
The image forming controller receives compression-encoded code information from the host PC, and performs a decoding process 501 to decompress RGB multilevel image information. The image forming controller performs a color process 502 such as CSC or gamma correction to convert the RGB multilevel image information into multilevel data of ink colors (e.g., C, M, Y, and K). Further, the image forming controller performs a pseudo halftone process 503 using error diffusion or dithering to convert the multilevel data into binary data (image forming data) for each ink color. In this way, multilevel image data is converted into image forming data at a level (binary in this example) that can be output from the image forming engine (print head).
When image data processes such as the decoding process 501, the color process 502, and the pseudo halftone process 503 are executed in the system LSI chip serving as the core for controlling the entire system, the main memory connected outside the system LSI chip is desirably shared in terms of cost reduction.
However, when giving attention to the process of a given pixel in a decoding process for one raster that refers to pixels of one upper raster in order to perform decoding for one raster, the memory (reference raster memory) is accessed to read a reference pixel value for each color to be processed. For example, when processing three, R, G, and B colors, the reference raster memory needs to be accessed a total of three times. That is, for example, when the process is done at an operating frequency of 200 MHz in four cycles per pixel, a requested access speed is as high as (200 MHz/4 cycles)×3×16 bits=300 Mbytes/S.
Many problems arise from access to the reference raster memory at a very high access speed in the decoding process. The first problem is the influence on the decoding process itself. The decoding process performance may not be fully exploited owing to access to the reference raster memory at a very high access speed. The second problem is the influence on the entire system. In a system in which the main memory is physically shared between a memory necessary for other data processes and system control, and the reference raster memory for the purpose of cost reduction, frequent access to the reference raster memory space may influence other data processes and system control.
To prevent these problems, there is proposed a configuration which adopts an on-chip buffer capable of storing a reference raster when a high-speed process is required, and suppresses access to the main memory to implement high performance (see, e.g., Japanese Patent No. 3083493).
Recently, functional integration has further proceeded upon requests for downsizing of the apparatus and cost reduction. Apparatuses in which a single system LSI chip implements main functions of an image forming controller are growing in number. More specifically, one system LSI chip performs network control between the apparatus and a host PC, printer language analysis, a decoding process, a color process, and a pseudo halftone process. Input/output of data associated with the generation of image forming data, which is typified by access to the reference raster memory to read a reference pixel value in a decoding process, uses a very large bandwidth. For this reason, a demand has arisen for building an optimal memory system of the system LSI chip in terms of high performance and cost reduction.
As described above, the configuration having an on-chip buffer capable of storing a reference raster can suppress the bandwidth consumption of the main memory. However, a large-format printer having a large printing width increases the chip size and cost. Assuming that R, G, and B each are made up of 16 bits when the on-chip buffer stores an upper reference raster in the decoding process, the necessary memory capacity is the number of pixels of one raster×48 bits. Processing high-resolution image information such as a text or line image requires an especially large memory capacity. For example, a memory capacity as large as 3.3 Mbits is necessary to cope with a resolution of 1,200 dpi and a maximum printing width of 60 inches.